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D at a S he e t, V 2. 0 , M ay 20 0 1
C 1 6 4C I/ SI C 1 6 4C L/ SL
16 -B it S in gl e -C hi p Mi cro c on tro ll e r
Mi cro c on tr ol le rs
Never
stop
thinking.
Edition 2001-05 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany
(c) Infineon Technologies AG 2001. All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D at a S he e t, V 2. 0 , M ay 20 0 1
C 1 6 4C I/ SI C 1 6 4C L/ SL
16 -B it S in gl e -C hi p Mi cro c on tro ll e r
Mi cro c on tr ol le rs
Never
stop
thinking.
C164CI Revision History: Previous Version: 2001-05 1999-08 1998-02 04.97 (Preliminary) (Advance Information) V2.0
Page All 1 1 et al. 1 1, 12, 73 2 10 21 22f 29, 30 37 41 to 73
1)
Subjects (major changes since last revision)1) Converted to Infineon layout Operating frequency up to 25 MHz References to Flash removed Timer Unit with three timers On-chip XRAM described Derivative table updated Supply voltage is 5 V Functionality of reduced CAPCOM6 corrected Timer description improved Sections "Oscillator Watchdog" and "Power Management" added POCON reset values adjusted Parameter section reworked
These changes refer to the last two versions. Version 1998-02 covers OTP and ROM derivatives, while version 1999-08 ist the most recent one.
Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com
16-Bit Single-Chip Microcontroller C166 Family C164CI/SI, C164CL/SL
C164CI
* High Performance 16-bit CPU with 4-Stage Pipeline - 80 ns Instruction Cycle Time at 25 MHz CPU Clock - 400 ns Multiplication (16 x 16 bit), 800 ns Division (32 / 16 bit) - Enhanced Boolean Bit Manipulation Facilities - Additional Instructions to Support HLL and Operating Systems - Register-Based Design with Multiple Variable Register Banks - Single-Cycle Context Switching Support - 16 MBytes Total Linear Address Space for Code and Data - 1024 Bytes On-Chip Special Function Register Area * 16-Priority-Level Interrupt System with 32 Sources, Sample-Rate down to 40 ns * 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) * Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input * On-Chip Memory Modules - 2 KBytes On-Chip Internal RAM (IRAM) - 2 KBytes On-Chip Extension RAM (XRAM) - up to 64 KBytes On-Chip Program Mask ROM or OTP Memory * On-Chip Peripheral Modules - 8-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 s - 8-Channel General Purpose Capture/Compare Unit (CAPCOM2) - Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel) - Multi-Functional General Purpose Timer Unit with 3 Timers - Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous) - On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects (Full CAN/Basic CAN) - On-Chip Real Time Clock * Up to 4 MBytes External Address Space for Code and Data - Programmable External Bus Characteristics for Different Address Ranges - Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width - Four Optional Programmable Chip-Select Signals * Idle, Sleep, and Power Down Modes with Flexible Power Management * Programmable Watchdog Timer and Oscillator Watchdog * Up to 59 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
Data Sheet 1 V2.0, 2001-05
C164CI/SI C164CL/SL
* Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards * On-Chip Bootstrap Loader * 80-Pin MQFP Package, 0.65 mm pitch This document describes several derivatives of the C164 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. Table 1 Derivative1) SAK-C164CI-8R[25]M SAF-C164CI-8R[25]M SAK-C164SI-8R[25]M SAF-C164SI-8R[25]M SAK-C164CL-8R[25]M SAF-C164CL-8R[25]M SAK-C164SL-8R[25]M SAF-C164SL-8R[25]M SAK-C164CL-6R[25]M SAF-C164CL-6R[25]M SAK-C164SL-6R[25]M SAF-C164SL-6R[25]M SAK-C164CI-L[25]M SAF-C164CI-L[25]M SAK-C164CI-8EM SAF-C164CI-8EM
1)
C164CI Derivative Synopsis Program Memory 64 KByte ROM 64 KByte ROM 64 KByte ROM 64 KByte ROM 48 KByte ROM 48 KByte ROM --64 KByte OTP CAPCOM6 Full function Full function CAN Interf. CAN1 --Operating Frequency 20 MHz, [25 MHz] 20 MHz, [25 MHz] 20 MHz, [25 MHz] 20 MHz, [25 MHz] 20 MHz, [25 MHz] 20 MHz, [25 MHz] 20 MHz, [25 MHz] 20 MHz
Reduced fct. CAN1 Reduced fct. --Reduced fct. CAN1 Reduced fct. --Full function Full function CAN1 CAN1
This Data Sheet is valid for ROM(less) devices starting with and including design step AB, and for OTP devices starting with and including design step DA.
For simplicity all versions are referred to by the term C164CI throughout this document.
Data Sheet
2
V2.0, 2001-05
C164CI/SI C164CL/SL
Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: * the derivative itself, i.e. its function set, the temperature range, and the supply voltage * the package and the type of delivery. For the available ordering codes for the C164CI please refer to the "Product Catalog Microcontrollers", which summarizes all available microcontroller variants. Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code. Introduction The C164CI derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers are especially suited for cost sensitive applications. They combine high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM or OTP, internal RAM, and extension RAM.
VAREF VAGND VDD
VSS
XTAL1 XTAL2 RSTIN RSTOUT NMI EA ALE RD WR/WRL
Port 0 16 Bit Port 1 16 Bit
C164CI
Port 3 9 Bit Port 4 6 Bit Port 8 4 Bit Port 5 8 Bit
MCL04869
Figure 1
Data Sheet
Logic Symbol
3 V2.0, 2001-05
C164CI/SI C164CL/SL
Pin Configuration (top view)
P5.3/AN3 P5.2/AN2 P5.1/AN1 P5.0/AN0 P8.3/CC19IO/* P8.2/CC18IO/* P8.1/CC17IO/* P8.0/CC16IO/* NMI RSTOUT RSTIN P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11/EXIN/T7IN P1H.2/A10/CC6POS2/EX2IN P1H.1/A9/CC6POS1/EX1IN
VAGND
VAREF
P5.4/AN4/T2EUD P5.5/AN5/T4EUD P5.6/AN6/T2IN P5.7/AN7/T4IN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VDD
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
VSS VDD
P3.4/T3EUD P3.6/T3IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P3.12/BHE/WRH P3.13/SCLK P3.15/CLKOUT/FOUT P4.0/A16/CS3 P4.1/A17/CS2 P4.2/A18/CS1
P4.3/A19/CS0 */P4.5/A20 */P4.6/A21 RD WR/WRL ALE Vpp/EA P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 P0H.0/AD8 P0H.1/AD9 P0H.2/AD10
VDD
VDD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
VSS
P1H.0/A8/CC6POS0/EX0IN P1L.7/A7/CTRAP P1L.6/A6/COUT63
VSS
XTAL1 XTAL2
VDD
P1L.5/A5/COUT62 P1L.4/A4/CC62 P1L.3/A3/COUT61 P1L.2/A2/CC61 P1L.1/A1/COUT60 P1L.0/A0/CC60 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11
C164CI
VSS
MCP04870
Figure 2 *) The marked pins of Port 4 and Port 8 can have CAN interface lines assigned to them. Table 2 on the pages below lists the possible assignments. The marked input signals are available only in devices with a full-function CAPCOM6. They are not available in devices with a reduced-function CAPCOM6.
Data Sheet
4
V2.0, 2001-05
C164CI/SI C164CL/SL
Table 2 Symbol Pin No. P5
Pin Definitions and Functions Input Outp. I Function Port 5 is an 8-bit input-only port with Schmitt-Trigger charact. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4, T2EUD GPT1 Timer T2 Ext. Up/Down Ctrl. Inp. AN5, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp. AN6, T2IN GPT1 Timer T2 Input for Count/Gate/Reload/Capture AN7, T4IN GPT1 Timer T4 Input for Count/Gate/Reload/Capture Port 3 is a 9-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: T3EUD GPT1 Timer T3 External Up/Down Control Input T3IN GPT1 Timer T3 Count/Gate Input MRST SSC Master-Receive/Slave-Transmit Inp./Outp. MTSR SSC Master-Transmit/Slave-Receive Outp./Inp. TxD0 ASC0 Clock/Data Output (Async./Sync.) RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.) External Memory High Byte Enable Signal, BHE External Memory High Byte Write Strobe WRH SCLK SSC Master Clock Output / Slave Clock Input. CLKOUT System Clock Output (= CPU Clock), FOUT Programmable Frequency Output
P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P3
76 77 78 79 2 3 4 5
I I I I I I I I IO
P3.4 P3.6 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.15
8 9 10 11 12 13 14 15 16
I I I/O I/O O I/O O O I/O O O
Data Sheet
5
V2.0, 2001-05
C164CI/SI C164CL/SL
Table 2 Symbol Pin No. P4
Pin Definitions and Functions (cont'd) Input Outp. IO Function Port 4 is a 6-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 4 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special). Port 4 can be used to output the segment address lines, the optional chip select lines, and for serial interface lines:1) A16 Least Significant Segment Address Line, CS3 Chip Select 3 Output A17 Segment Address Line, Chip Select 2 Output CS2 A18 Segment Address Line, Chip Select 1 Output CS1 A19 Segment Address Line, Chip Select 0 Output CS0 A20 Segment Address Line, CAN1_RxD CAN 1 Receive Data Input A21 Most Significant Segment Address Line, CAN1_TxD CAN 1 Transmit Data Output External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes.
P4.0 P4.1 P4.2 P4.3 P4.5 P4.6 RD WR/ WRL
17 18 19 22 23 24 25 26
O O O O O O O O O I O O O O
ALE
27
O
Data Sheet
6
V2.0, 2001-05
C164CI/SI C164CL/SL
Table 2 Symbol Pin No. EA/VPP 28
Pin Definitions and Functions (cont'd) Input Outp. I Function External Access Enable pin. A low level at this pin during and after Reset forces the C164CI to latch the configuration from PORT0 and pin RD, and to begin instruction execution out of external memory. A high level forces the C164CI to latch the configuration from pins RD and ALE, and to begin instruction execution out of the internal program memory. "ROMless" versions must have this pin tied to `0'. Note: This pin also accepts the programming voltage for the OTP derivatives.
PORT0 IO P0L.0-7 2936 P0H.0-7 37-39, 42-46
PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0 - P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15
Data Sheet
7
V2.0, 2001-05
C164CI/SI C164CL/SL
Table 2 Symbol Pin No.
Pin Definitions and Functions (cont'd) Input Outp. Function PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alt. functions: CC60 CAPCOM6: Input / Output of Channel 0 COUT60 CAPCOM6: Output of Channel 0 CC61 CAPCOM6: Input / Output of Channel 1 COUT61 CAPCOM6: Output of Channel 1 CC62 CAPCOM6: Input / Output of Channel 2 COUT62 CAPCOM6: Output of Channel 2 COUT63 Output of 10-bit Compare Channel CAPCOM6: Trap Input CTRAP CTRAP is an input pin with an internal pullup resistor. A low level on this pin switches the compare outputs of the CAPCOM6 unit to the logic level defined by software. CC6POS0 CAPCOM6: Position 0 Input, **) EX0IN Fast External Interrupt 0 Input CC6POS1 CAPCOM6: Position 1 Input, **) EX1IN Fast External Interrupt 1 Input CC6POS2 CAPCOM6: Position 2 Input, **) EX2IN Fast External Interrupt 2 Input EX3IN Fast External Interrupt 3 Input, T7IN CAPCOM2: Timer T7 Count Input CC24IO CAPCOM2: CC24 Capture Inp./Compare Outp. CC25IO CAPCOM2: CC25 Capture Inp./Compare Outp. CC26IO CAPCOM2: CC26 Capture Inp./Compare Outp. CC27IO CAPCOM2: CC27 Capture Inp./Compare Outp. Note: The marked (**) input signals are available only in devices with a full function CAPCOM6.
PORT1 IO P1L.0-7 47-52, 57-59 P1H.0-7 59, 62-68
P1L.0 P1L.1 P1L.2 P1L.3 P1L.4 P1L.5 P1L.6 P1L.7
47 48 49 50 51 52 57 58
I/O O I/O O I/O O O I
P1H.0 P1H.1 P1H.2 P1H.3 P1H.4 P1H.5 P1H.6 P1H.7
59 62 63 64 65 66 67 68
I I I I I I I I/O I/O I/O I/O
Data Sheet
8
V2.0, 2001-05
C164CI/SI C164CL/SL
Table 2 Symbol Pin No. XTAL2 XTAL1 54 55
Pin Definitions and Functions (cont'd) Input Outp. O I Function XTAL2: XTAL1: Output of the oscillator amplifier circuit. Input to the oscillator amplifier and input to the internal clock generator To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C164CI. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. A spike filter suppresses input pulses <10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table. Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C164CI to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally.
RSTIN
69
I/O
RST OUT
70
O
NMI
71
I
Data Sheet
9
V2.0, 2001-05
C164CI/SI C164CL/SL
Table 2 Symbol Pin No. P8
Pin Definitions and Functions (cont'd) Input Outp. IO Function Port 8 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 8 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 8 is selectable (TTL or special). Port 8 pins provide inputs/ outputs for CAPCOM2 and serial interface lines.1) CC16IO CAPCOM2: CC16 Capture Inp./Compare Outp., CAN1_RxD CAN 1 Receive Data Input CC17IO CAPCOM2: CC17 Capture Inp./Compare Outp., CAN1_TxD CAN 1 Transmit Data Output CC18IO CAPCOM2: CC18 Capture Inp./Compare Outp., CAN1_RxD CAN 1 Receive Data Input CC19IO CAPCOM2: CC19 Capture Inp./Compare Outp., CAN1_TxD CAN 1 Transmit Data Output Reference voltage for the A/D converter. Reference ground for the A/D converter. Digital Supply Voltage: +5 V during normal operation and idle mode. 2.5 V during power down mode. Digital Ground.
P8.0 P8.1 P8.2 P8.3
72 73 74 75 1 80
I/O I I/O O I/O I I/O O - -
VAREF VAGND VDD
7, 21, - 40, 53, 61 6, 20, - 41, 56, 60
VSS
1)
The CAN interface lines are assigned to ports P4 and P8 under software control. Within the CAN module several assignments can be selected.
Note: The following behavioural differences must be observed when the bidirectional reset is active: * Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset. * The reset indication flags always indicate a long hardware reset. * The PORT0 configuration is treated as if it were a hardware reset. In particular, the bootstrap loader may be activated when P0L.4 is low. * Pin RSTIN may only be connected to external reset devices with an open drain output driver. * A short hardware reset is extended to the duration of the internal reset sequence.
Data Sheet
10
V2.0, 2001-05
C164CI/SI C164CL/SL
Functional Description The architecture of the C164CI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C164CI. Note: All time specifications refer to a CPU clock of 25 MHz (see definition in the AC Characteristics section).
Data
Dual Port
ProgMem
ROM: 48/64 OTP: 64 KByte
32
Instr. / Data
C166-Core
16
IRAM
Internal RAM 2 KByte
CPU
16
Data
16
XRAM
2 KByte
External Instr. / Data
Osc / PLL
PEC
XTAL
Interrupt Controller 16-Level Priority 16
On-Chip XBUS (16-Bit Demux)
RTC
WDT
Interrupt Bus 16
Peripheral Data Bus
CAN
Rev 2.0B active
ADC
10-Bit 8 Channels
ASC0
(USART)
SSC
(SPI)
GPT1
T2 T3 T4
CCOM2 CCOM6
T7 T8 T12 T13
Port 1
EBC
6
XBUS Control External Bus Control
Port 0 16 Port 5 8
Port 4
16
BRGen
BRGen Port 3 9 Port 8 4
MCB04323_4ci
Figure 3
Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourth bus, the XBUS, connects external resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3). The XBUS resources (XRAM, CAN) of the C164CI can be enabled or disabled during initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules that are disabled consume neither address space nor port pins.
Data Sheet
11
V2.0, 2001-05
C164CI/SI C164CL/SL
Memory Organization The memory space of the C164CI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. The C164CI incorporates 64 KBytes of on-chip OTP memory or 64/48 KBytes of on-chip mask-programmable ROM (not in the ROM-less derivative, of course) for code or constant data. The lower 32 KBytes of the on-chip ROM/OTP can be mapped either to segment 0 or segment 1. The OTP memory can be programmed by the CPU itself (in system, e.g. during booting) or directly via an external interface (e.g. before assembly). The programming time is approx. 100 s per word. An external programming voltage VPP = 11.5 V must be supplied for this purpose (via pin EA/VPP). 2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 x 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family. 2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed. In order to meet the needs of designs where more memory is required than is provided on chip, up to 4 MBytes of external RAM and/or ROM can be connected to the microcontroller.
Data Sheet
12
V2.0, 2001-05
C164CI/SI C164CL/SL
External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: - - - - 16-/18-/20-/22-bit Addresses, 16-bit Data, Demultiplexed 16-/18-/20-/22-bit Addresses, 16-bit Data, Multiplexed 16-/18-/20-/22-bit Addresses, 8-bit Data, Multiplexed 16-/18-/20-/22-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/ output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which control the access to different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 4 external CS signals (3 windows plus default) can be generated in order to save external glue logic. The C164CI offers the possibility to switch the CS outputs to an unlatched mode. In this mode the internal filter logic is switched off and the CS signals are directly generated from the address. The unlatched CS mode is enabled by setting CSCFG (SYSCON.6). For applications which require less than 4 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case Port 4 outputs four, two, or no address lines at all. It outputs all 6 address lines, if an address space of 4 MBytes is used. Note: When the on-chip CAN Module is used with the interface lines assigned to Port 4, the CAN lines override the segment address lines and the segment address output on Port 4 is therefore limited to 4 bits i.e. address lines A19 ... A16.
Data Sheet
13
V2.0, 2001-05
C164CI/SI C164CL/SL
Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C164CI's instructions can be executed in just one machine cycle which requires 2 CPU clocks (4 TCL). For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline optimization, the socalled `Jump Cache', reduces the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
CPU SP STKOV STKUN Exec. Unit Instr. Ptr. Instr. Reg. 32 ROM 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Page Ptr. MDH MDL Mul/Div-HW Bit-Mask Gen ALU (16-bit) Barrel - Shifter Context Ptr. ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. R0 Registers
16 Internal RAM R15
General Purpose
R15
R0
16
MCB02147
Figure 4
CPU Block Diagram
Data Sheet
14
V2.0, 2001-05
C164CI/SI C164CL/SL
The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C164CI instruction set which includes the following instruction classes: - - - - - - - - - - - - Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands.
Data Sheet
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Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C164CI is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C164CI supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C164CI has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. Table 3 shows all of the possible C164CI interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. Note: Interrupt nodes which are not used by associated peripherals, may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xIR).
Data Sheet
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Table 3
C164CI Interrupt Nodes Enable Flag CC8IE CC9IE CC10IE CC11IE T2IE T3IE T4IE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE CC16IE CC17IE CC18IE CC19IE CC24IE CC25IE CC26IE CC27IE T7IE T8IE CC6IE XP0IE XP3IE
17
Source of Interrupt or Request PEC Service Request Flag Fast External Interrupt 0 CC8IR Fast External Interrupt 1 CC9IR Fast External Interrupt 2 CC10IR Fast External Interrupt 3 CC11IR GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 A/D Conversion Complete A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Timer 7 CAPCOM Timer 8 CAPCOM6 Interrupt CAN Interface 1 PLL/OWD and RTC
Data Sheet
Interrupt Vector CC8INT CC9INT CC10INT CC11INT T2INT T3INT T4INT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT CC16INT CC17INT CC18INT CC19INT CC24INT CC25INT CC26INT CC27INT T7INT T8INT CC6INT XP0INT XP3INT
Vector Location 00'0060H 00'0064H 00'0068H 00'006CH 00'0088H 00'008CH 00'0090H 00'00A0H 00'00A4H 00'00A8H 00'011CH 00'00ACH 00'00B0H 00'00B4H 00'00B8H 00'00BCH 00'00C0H 00'00C4H 00'00C8H 00'00CCH 00'00E0H 00'00E4H 00'00E8H 00'00ECH 00'00F4H 00'00F8H 00'00FCH 00'0100H 00'010CH
Trap Number 18H 19H 1AH 1BH 22H 23H 24H 28H 29H 2AH 47H 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 38H 39H 3AH 3BH 3DH 3EH 3FH 40H 43H
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T2IR T3IR T4IR ADCIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR CC16IR CC17IR CC18IR CC19IR CC24IR CC25IR CC26IR CC27IR T7IR T8IR CC6IR XP0IR XP3IR
C164CI/SI C164CL/SL
Table 3
C164CI Interrupt Nodes (cont'd) Enable Flag T12IE T13IE CC6EIE Interrupt Vector T12INT T13INT CC6EINT Vector Location 00'0134H 00'0138H 00'013CH Trap Number 4DH 4EH 4FH
Source of Interrupt or Request PEC Service Request Flag CAPCOM 6 Timer 12 CAPCOM 6 Timer 13 T12IR T13IR
CAPCOM 6 Emergency CC6EIR
Data Sheet
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The C164CI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Table 4 shows all of the possible exceptions or error conditions that can arise during runtime: Table 4 Hardware Trap Summary Trap Flag - RESET RESET RESET 00'0000H 00'0000H 00'0000H 00H 00H 00H 02H 04H 06H 0AH 0AH 0AH 0AH 0AH [0BH - 0FH] III III III II II II I I I I I - Current CPU Priority Trap Vector Vector Location Trap Number Trap Priority
Exception Condition Reset Functions: - Hardware Reset - Software Reset - W-dog Timer Overflow
Class A Hardware Traps: - Non-Maskable Interrupt NMI - Stack Overflow STKOF - Stack Underflow STKUF Class B Hardware Traps: - Undefined Opcode - Protected Instruction Fault - Illegal Word Operand Access - Illegal Instruction Access - Illegal External Bus Access Reserved Software Traps - TRAP Instruction
NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H 00'0028H 00'0028H 00'0028H 00'0028H 00'0028H [2CH - 3CH]
UNDOPC BTRAP PRTFLT BTRAP ILLOPA ILLINA ILLBUS - - BTRAP BTRAP BTRAP - -
Any Any [00'0000H - [00H - 00'01FCH] 7FH] in steps of 4H
Data Sheet
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The Capture/Compare Unit CAPCOM2 The general purpose CAPCOM2 unit supports generation and control of timing sequences on up to 8 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for the capture/compare register array. Each dual purpose capture/compare register, which may be individually allocated to either CAPCOM timer and programmed for capture or compare function, has one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`capture'd) into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Table 5 Mode 0 Mode 1 Mode 2 Mode 3 Double Register Mode Compare Modes (CAPCOM2) Function Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated Two registers operate on one pin; pin toggles on each compare match; several compare events per timer period are possible. Registers CC16 & CC24 (c) pin CC16IO Registers CC17 & CC25 (c) pin CC17IO Registers CC18 & CC26 (c) pin CC18IO Registers CC19 & CC27 (c) pin CC19IO
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Compare Modes
Data Sheet
C164CI/SI C164CL/SL
The Capture/Compare Unit CAPCOM6 The CAPCOM6 unit supports generation and control of timing sequences on up to three 16-bit capture/compare channels plus one 10-bit compare channel. In compare mode the CAPCOM6 unit provides two output signals per channel which have inverted polarity and non-overlapping pulse transitions. The compare channel can generate a single PWM output signal and is further used to modulate the capture/ compare output signals. In capture mode the contents of compare timer 12 is stored in the capture registers upon a signal transition at pins CCx. Compare timers T12 (16-bit) and T13 (10-bit) are free running timers which are clocked by the prescaled CPU clock.
Period Register T12P
Mode Select Register CC6MSEL
Trap Register
CTRAP
Prescaler
Offset Register T12OF
CC Channel 0 CC60
CC60 COUT60 Port Control Logic CC61 COUT61 CC62 COUT62
fCPU
Control
Compare Timer T12 16-Bit
CC Channel 1 CC61 CC Channel 2 CC62
Control Register CTCON
Prescaler
fCPU
Compare Timer T13 10-Bit
Compare Register CMP13 Block Commutation Control CC6MCON.H
COUT63 CC6POS0 CC6POS1 CC6POS2
MCB04109
Period Register T13P
The timer registers (T12, T13) are not directly accessible. The period and offset registers are loading a value into the timer registers. The shaded blocks are available in the full function module only.
Figure 5
CAPCOM6 Block Diagram
For motor control applications both subunits may generate versatile multichannel PWM signals which are basically either controlled by compare timer 12 or by a typical hall sensor pattern at the interrupt inputs (block commutation). Note: Multichannel signal generation is provided only in devices with a full CAPCOM6.
Data Sheet 21 V2.0, 2001-05
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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates three 16-bit timers. Each timer may operate independently in a number of different modes, or may be concatenated with another timer. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking. In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL.
Data Sheet
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T2EUD fCPU T2IN 2n : 1 T2 Mode Control
U/D GPT1 Timer T2 Interrupt Request (T2IR)
Reload Capture Interrupt Request (T3IR) T3 Mode Control Toggle FF GPT1 Timer T3 U/D Other Timers Capture Reload T3OTL
fCPU
2n : 1
T3IN
T3EUD
T4IN fCPU T4EUD
n = 3 ... 10
2n : 1
T4 Mode Control
GPT1 Timer T4 U/D
Interrupt Request (T4IR)
Mct04825_4.vsd
Figure 6
Block Diagram of GPT1
Data Sheet
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Real Time Clock The Real Time Clock (RTC) module of the C164CI consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked with the on-chip oscillator frequency divided by 32 via a separate clock driver (fRTC = fOSC/32) and is therefore independent from the selected clock generation mode of the C164CI. All timers count up. The RTC module can be used for different purposes: * System clock to determine the current time and date * Cyclic time based interrupt * 48-bit timer for long term measurements
T14REL Reload T14 8:1 f RTC Interrupt Request RTCH RTCL
MCD04432
Figure 7
RTC Block Diagram
Note: The registers associated with the RTC are not affected by a reset in order to maintain the correct system time even when intermediate resets are executed.
Data Sheet
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A/D Converter For analog signal measurement, a 10-bit A/D converter with 8 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less than 8 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C164CI supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels (standard or extension) are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. After each reset and also during normal operation the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the A/D converter. In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via register P5DIDIS (Port 5 Digital Input Disable).
Data Sheet
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Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 781 Kbit/s and half-duplex synchronous communication at up to 3.1 Mbit/s (@ 25 MHz CPU clock). A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The SSC supports full-duplex synchronous communication at up to 6.25 Mbit/s (@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 3 separate interrupt vectors are provided. The SSC transmits or receives characters of 2 ... 16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data.
Data Sheet
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CAN-Module The integrated CAN-Module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The module provides Full CAN functionality on up to 15 message objects. Message object 15 may be configured for Basic CAN functionality. Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes. The bit timing is derived from the XCLK and is programmable up to a data rate of 1 Mbit/ s. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus transceiver. The interface pins are assigned via software. Note: When the CAN interface is assigned to Port 4, the respective segment address lines on Port 4 cannot be used. This will limit the external address space. Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/ 256. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 20 s and 336 ms can be monitored (@ 25 MHz). The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz).
Data Sheet
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Parallel Ports The C164CI provides up to 59 I/O lines which are organized into five input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. During the internal reset, all port pins are configured as inputs. The input threshold of Port 3, Port 4, and Port 8 is selectable (TTL or CMOS like), where the special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports. All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A21/19/17 ... A16 and the optional chip select signals in systems where segmentation is enabled to access more than 64 KBytes of memory. Ports P1L, P1H, and P8 are associated with the capture inputs or compare outputs of the CAPCOM units and/or serve as external interrupt inputs. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE/WRH, and the system clock output CLKOUT (or the programmable frequency output FOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. The edge characteristics (transition time) and driver characteristics (output current) of the C164CI's port drivers can be selected via the Port Output Control registers (POCONx).
Data Sheet
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Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and supplies the CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic frequency. In direct drive mode the PLL base frequency is used directly (fCPU = 2 ... 5 MHz). In prescaler mode the PLL base frequency is divided by 2 (fCPU = 1 ... 2.5 MHz). Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset. The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON. In this case (OWDDIS = `1') the PLL remains idle and provides no clock signal, while the CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also no interrupt request will be generated in case of a missing oscillator clock. Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time. Thus the oscillator watchdog may also be disabled via hardware by (externally) pulling the RD line low upon a reset, similar to the standard reset configuration via PORT0.
Data Sheet
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Power Management The C164CI provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): * Power Saving Modes switch the C164CI into a special operating mode (control via instructions). Idle Mode stops the CPU while the peripherals can continue to operate. Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may optionally continue running). Sleep Mode can be terminated by external interrupt signals. * Clock Generation Management controls the distribution and the frequency of internal and external clock signals (control via register SYSCON2). Slow Down Mode lets the C164CI run at a CPU clock frequency of fOSC/1 ... 32 (half for prescaler operation) which drastically reduces the consumed power. The PLL can be optionally disabled while operating in Slow Down Mode. External circuitry can be controlled via the programmable frequency output FOUT. * Peripheral Management permits temporary disabling of peripheral modules (control via register SYSCON3). Each peripheral can separately be disabled/enabled. A group control option disables a major part of the peripheral set by setting one single bit. The on-chip RTC supports intermittend operation of the C164CI by generating cyclic wakeup signals. This offers full performance to quickly react on action requests while the intermittend sleep phases greatly reduce the average power consumption of the system.
Data Sheet
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Instruction Set Summary Table 6 lists the instructions of the C164CI in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "C166 Family Instruction Set Manual". This document also provides a detailled description of each instruction. Table 6 Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR
Data Sheet
Instruction Set Summary Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR
31
Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2
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Table 6
Instruction Set Summary (cont'd) Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack und update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 2/4 2/4 2/4 4 4 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2
Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP
Data Sheet
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V2.0, 2001-05
C164CI/SI C164CL/SL
Special Function Registers Overview Table 7 lists all SFRs which are implemented in the C164CI in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Registers within on-chip X-peripherals are marked with the letter "X" in column "Physical Address". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Table 7 Name ADCIC ADCON ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC C164CI Registers, Ordered by Name Physical Address b FF98H b FFA0H FEA0H F0A0H FE18H FE1AH FE1CH FE1EH b FF9AH 8-Bit Description Addr. CCH D0H 50H E 50H 0CH 0DH 0EH 0FH CDH 86H 8AH 8BH 8CH 8DH X --X --X --X --X --X --A/D Converter End of Conversion Interrupt Control Register A/D Converter Control Register A/D Converter Result Register A/D Converter 2 Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 A/D Converter Overrun Error Interrupt Control Register Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 CAN1 Bit Timing Register CAN1 Control / Status Register CAN1 Global Mask Short CAN Lower Global Mask Long CAN Lower Mask of Last Message
33
Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H UUUUH XX01H UFUUH UUUUH UUUUH
V2.0, 2001-05
BUSCON0 b FF0CH BUSCON1 b FF14H BUSCON2 b FF16H BUSCON3 b FF18H BUSCON4 b FF1AH C1BTR C1CSR C1GMS C1LARn C1LGML C1LMLM
Data Sheet
EF04H EF00H EF06H EFn4H EF0AH EF0EH
CAN Lower Arbitration Register (msg. n) UUUUH
C164CI/SI C164CL/SL
Table 7 Name C1MCFGn C1MCRn C1PCIR C1UARn C1UGML C1UMLM CC10IC CC11IC CC16 CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC CC20 CC20IC CC21 CC21IC CC22 CC22IC CC23 CC23IC CC24 CC24IC CC25 CC25IC CC26
Data Sheet
C164CI Registers, Ordered by Name (cont'd) Physical Address EFn6H EFn0H EF02H EFn2H EF08H EF0CH b FF8CH b FF8EH FE60H b F160H FE62H b F162H FE64H b F164H FE66H b F166H FE68H b F168H 8-Bit Description Addr. X --X --X --X --X --X --C6H C7H 30H E B0H 31H E B1H 32H E B2H 33H E B3H 34H CAN Message Configuration Register (msg. n) CAN1 Port Control / Interrupt Register CAN Upper Global Mask Long CAN Upper Mask of Last Message External Interrupt 2 Control Register External Interrupt 3 Control Register CAPCOM Register 16 CAPCOM Reg. 16 Interrupt Ctrl. Reg. CAPCOM Register 17 CAPCOM Reg. 17 Interrupt Ctrl. Reg. CAPCOM Register 18 CAPCOM Reg. 18 Interrupt Ctrl. Reg. CAPCOM Register 19 CAPCOM Reg. 19 Interrupt Ctrl. Reg. CAPCOM Register 20 CAPCOM Reg. 20 Interrupt Ctrl. Reg. CAPCOM Register 21 CAPCOM Reg. 21 Interrupt Ctrl. Reg. CAPCOM Register 22 CAPCOM Reg. 22 Interrupt Ctrl. Reg. CAPCOM Register 23 CAPCOM Reg. 23 Interrupt Ctrl. Reg. CAPCOM Register 24 CAPCOM Reg. 24 Interrupt Ctrl. Reg. CAPCOM Register 25 CAPCOM Reg. 25 Interrupt Ctrl. Reg. CAPCOM Register 26
34
Reset Value UUH
CAN Message Control Register (msg. n) UUUUH XXXXH UUUUH UUUUH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H
V2.0, 2001-05
CAN Upper Arbitration Register (msg. n) UUUUH
E B4H FE6AH 35H b F16AH E B5H FE6CH b F16CH 36H E B6H FE6EH 37H b F16EH E B7H FE70H b F170H FE72H b F172H FE74H 38H E B8H 39H E B9H 3AH
C164CI/SI C164CL/SL
Table 7 Name CC26IC CC27 CC27IC CC28 CC28IC CC29 CC29IC CC30 CC30IC CC31 CC31IC CC60 CC61 CC62 CC6EIC CC6CIC CC6MIC CC6MSEL CC8IC CC9IC CCM4 CCM5 CCM6 CCM7 CMP13 CP CSP
C164CI Registers, Ordered by Name (cont'd) Physical Address b F174H FE76H b F176H FE78H b F178H FE7AH b F184H 8-Bit Description Addr. E BAH 3BH E BBH 3CH E BCH 3DH CAPCOM Reg. 26 Interrupt Ctrl. Reg. CAPCOM Register 27 CAPCOM Reg. 27 Interrupt Ctrl. Reg. CAPCOM Register 28 CAPCOM Reg. 28 Interrupt Ctrl. Reg. CAPCOM Register 29 CAPCOM Reg. 29 Interrupt Ctrl. Reg. CAPCOM Register 30 CAPCOM Reg. 30 Interrupt Ctrl. Reg. CAPCOM Register 31 CAPCOM Reg. 31 Interrupt Ctrl. Reg. CAPCOM 6 Register 0 CAPCOM 6 Register 1 CAPCOM 6 Register 2 CAPCOM 6 Emergency Interrrupt Control Register CAPCOM 6 Interrupt Control Register CAPCOM 6 Mode Control Register CAPCOM 6 Mode Interrupt Ctrl. Reg. CAPCOM 6 Mode Select Register External Interrupt 0 Control Register External Interrupt 1 Control Register CAPCOM Mode Control Register 4 CAPCOM Mode Control Register 5 CAPCOM Mode Control Register 6 CAPCOM Mode Control Register 7 CAPCOM 6 Timer 13 Compare Reg. CPU Context Pointer Register CPU Code Segment Pointer Register (8 bits, not directly writeable) Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00FFH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H FC00H 0000H
E C2H FE7CH 3EH b F18CH E C6H FE7EH b F194H FE30H FE32H FE34H b F188H b F17EH b FF36H F036H b FF88H b FF8AH b FF22H b FF24H b FF26H b FF28H FE36H FE10H FE08H 3FH E CAH 18H 19H 1AH E C4H E BFH 99H 9BH E 1BH C4H C5H 91H 92H 93H 94H 1BH 08H 04H
CC6MCON b FF32H
Data Sheet
35
V2.0, 2001-05
C164CI/SI C164CL/SL
Table 7 Name CTCON DP0H DP0L DP1H DP1L DP3 DP4 DP8 DPP0 DPP1 DPP2 DPP3 EXICON EXISEL FOCON IDCHIP IDMANUF IDMEM IDPROG IDMEM2 ISNC MDC MDH MDL ODP3 ODP4 ODP8 ONES OPAD OPCTRL
Data Sheet
C164CI Registers, Ordered by Name (cont'd) Physical Address b FF30H b F102H b F100H b F106H b F104H b FFC6H b FFCAH b FFD6H FE00H FE02H FE04H FE06H b F1C0H b F1DAH b FFAAH F07CH F07EH F07AH F078H F076H b F1DEH b FF0EH FE0CH FE0EH b F1C6H b F1CAH b F1D6H b FF1EH 8-Bit Description Addr. 98H E 81H E 80H E 83H E 82H E3H E5H EBH 00H 01H 02H 03H E E0H E EDH D5H E 3EH E 3FH E 3DH E 3CH E 3BH E EFH 87H 06H 07H E E3H E E5H E EBH 8FH CAPCOM 6 Compare Timer Ctrl. Reg. P0H Direction Control Register P0L Direction Control Register P1H Direction Control Register P1L Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 8 Direction Control Register CPU Data Page Pointer 0 Reg. (10 bits) CPU Data Page Pointer 1 Reg. (10 bits) CPU Data Page Pointer 2 Reg. (10 bits) CPU Data Page Pointer 3 Reg. (10 bits) External Interrupt Control Register External Interrupt Source Select Reg. Frequency Output Control Register Identifier Identifier Identifier Identifier Identifier Interrupt Subnode Control Register CPU Multiply Divide Control Register CPU Multiply Divide Reg. - High Word CPU Multiply Divide Reg. - Low Word Port 3 Open Drain Control Register Port 4 Open Drain Control Register Port 8 Open Drain Control Register Constant Value 1's Register (read only) OTP Progr. Interface Address Register OTP Progr. Interface Control Register
36
Reset Value 1010H 00H 00H 00H 00H 0000H 00H 00H 0000H 0001H 0002H 0003H 0000H 0000H 0000H XXXXH 1820H XXXXH XXXXH XXXXH 0000H 0000H 0000H 0000H 0000H 00H 00H FFFFH 0000H 0007H
V2.0, 2001-05
EDC2H X --EDC0H X ---
C164CI/SI C164CL/SL
Table 7 Name OPDAT P0H P0L P1H P1L P3 P4 P5 P5DIDIS P8 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PICON POCON0H POCON0L POCON1H POCON1L POCON20 POCON3 POCON4 POCON8 PSW RP0H RSTCON
Data Sheet
C164CI Registers, Ordered by Name (cont'd) Physical Address b FF02H b FF00H b FF06H b FF04H b FFC4H b FFC8H b FFA2H b FFA4H b FFD4H FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH FECEH b F1C4H F082H F080H F086H F084H F0AAH F08AH F08CH F092H b FF10H b F108H 8-Bit Description Addr. OTP Progr. Interface Data Register Port 0 High Reg. (Upper half of PORT0) Port 0 Low Reg. (Lower half of PORT0) Port 1 High Reg. (Upper half of PORT1) Port 1 Low Reg. (Lower half of PORT1) Port 3 Register Port 4 Register (7 bits) Port 5 Register (read only) Port 5 Digital Input Disable Register Port 8 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register Port Input Threshold Control Register Port P0H Output Control Register Port P0L Output Control Register Port P1H Output Control Register Port P1L Output Control Register Dedicated Pin Output Control Register Port P3 Output Control Register Port P4 Output Control Register Port P8 Output Control Register CPU Program Status Word System Startup Config. Reg. (Rd. only) Reset Control Register
37
Reset Value 0000H 00H 00H 00H 00H 0000H 00H XXXXH 0000H 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0011H 0011H 0011H 0011H 0000H 2222H 0010H 0022H 0000H XXH 00XXH
V2.0, 2001-05
EDC4H X --81H 80H 83H 82H E2H E4H D1H D2H EAH 60H 61H 62H 63H 64H 65H 66H 67H E E2H E 41H E 40H E 43H E 42H E 55H E 45H E 46H E 49H 88H
E 84H b F1E0H m ---
C164CI/SI C164CL/SL
Table 7 Name RTCH RTCL S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSCBR SSCCON SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN SYSCON
C164CI Registers, Ordered by Name (cont'd) Physical Address F0D6H F0D4H FEB4H b FFB0H b FF70H FEB2H b FF6EH b F19CH FEB0H b FF6CH FE12H F0B4H b FFB2H b FF76H F0B2H b FF74H F0B0H b FF72H FE14H FE16H b FF12H 8-Bit Description Addr. E 6BH E 6AH 5AH D8H B8H 59H B7H E CEH 58H B6H 09H E 5AH D9H BBH E 59H BAH E 58H B9H 0AH 0BH 89H E EEH E E8H E EAH RTC High Register RTC Low Register Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Ctrl. Reg. Serial Channel 0 Receive Buffer Reg. (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Serial Channel 0 Transmit Buffer Reg. (write only) Serial Channel 0 Transmit Interrupt Control Register CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer SSC Receive Interrupt Control Register SSC Transmit Buffer SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register CPU System Configuration Register 1 CPU System Configuration Register 2 CPU System Configuration Register 3 Reset Value no no 0000H 0000H 0000H XXXXH 0000H 0000H 0000H 0000H FC00H 0000H 0000H 0000H XXXXH 0000H 0000H 0000H FA00H FC00H
1)
0xx0H 0000H 0000H 0000H
SYSCON1 b F1DCH SYSCON2 b F1D0H SYSCON3 b F1D4H
Data Sheet
38
V2.0, 2001-05
C164CI/SI C164CL/SL
Table 7 Name T12IC T12OF T12P T13IC T13P T14 T14REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T7 T78CON T7IC T7REL T8 T8IC T8REL TFR TRCON WDT WDTCON XP0IC XP1IC
C164CI Registers, Ordered by Name (cont'd) Physical Address b F190H F034H F030H b F198H F032H F0D2H F0D0H FE40H b FF40H b FF60H FE42H b FF42H b FF62H FE44H b FF44H b FF64H F050H b FF20H b F17AH F054H F052H b F17CH F056H b FFACH b FF34H FEAEH FFAEH b F186H b F18EH 8-Bit Description Addr. E C8H E 1AH E 18H E CCH E 19H E 69H E 68H 20H A0H B0H 21H A1H B1H 22H A2H B2H E 28H 90H E BDH E 2AH E 29H E BEH E 2BH D6H 9AH 57H D7H E C3H E C7H CAPCOM 6 Timer 12 Interrupt Ctrl. Reg. CAPCOM 6 Timer 12 Offset Register CAPCOM 6 Timer 12 Period Register CAPCOM 6 Timer 13 Interrupt Ctrl. Reg. CAPCOM 6 Timer 13 Period Register RTC Timer 14 Register RTC Timer 14 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register CAPCOM Timer 7 Register CAPCOM Timer 7 and 8 Ctrl. Reg. CAPCOM Timer 7 Interrupt Ctrl. Reg. CAPCOM Timer 7 Reload Register CAPCOM Timer 8 Register CAPCOM Timer 8 Interrupt Ctrl. Reg. CAPCOM Timer 8 Reload Register Trap Flag Register CAPCOM 6 Trap Enable Ctrl. Reg. Watchdog Timer Register (read only) Watchdog Timer Control Register CAN1 Module Interrupt Control Register Unassigned Interrupt Control Reg.
2)
Reset Value 0000H 0000H 0000H 0000H 0000H no no 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 00XXH 0000H 00xxH 0000H 0000H
Data Sheet
39
V2.0, 2001-05
C164CI/SI C164CL/SL
Table 7 Name XP3IC ZEROS
1) 2)
C164CI Registers, Ordered by Name (cont'd) Physical Address b F19EH b FF1CH 8-Bit Description Addr. E CFH 8EH PLL/RTC Interrupt Control Register Constant Value 0's Register (read only) Reset Value 0000H 0000H
The system configuration is selected during reset. The reset value depends on the indicated reset source.
Note: The three registers of the OTP programming interface are, of course, only implemented in the OTP versions of the C164CI.
Data Sheet
40
V2.0, 2001-05
C164CI/SI C164CL/SL
Absolute Maximum Ratings Table 8 Parameter Storage temperature Junction temperature Voltage on VDD pins with respect to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Power dissipation Absolute Maximum Rating Parameters Symbol Limit Values min. max. 150 150 6.5 C C V - under bias - - - - -65 -40 -0.5 -0.5 -10 - Unit Notes
TST TJ VDD VIN
- -
VDD + 0.5 V
10 |100| mA mA
PDISS
-
1.5
W
-
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings.
Data Sheet
41
V2.0, 2001-05
C164CI/SI C164CL/SL
Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C164CI. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 9 Parameter Digital supply voltage Operating Condition Parameters Symbol Limit Values min. max. 5.5 5.5 0 - - - 0 -40 -40
1) 2)
Unit Notes V V V mA mA pF C C C Active mode,
VDD
4.75 2.51)
fCPUmax = 25 MHz
PowerDown mode Reference voltage Per pin2)3)
3)
Digital ground voltage Overload current Absolute sum of overload currents External Load Capacitance Ambient temperature
VSS IOV
|IOV|
5 50 100 70 85 125
CL TA
Pin drivers in default mode4)5) SAB-C164CI ... SAF-C164CI ... SAK-C164CI ...
Output voltages and output currents will be reduced when VDD leaves the range defined for active mode. Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits. Proper operation is not guaranteed if overload conditions occur on functional pins line XTAL1, RD, WR, etc. Not 100% tested, guaranteed by design and characterization. The timing is valid for pin drivers operating in default current mode (selected after reset). Reducing the output current may lead to increased delays or reduced driving capability (CL). The current ROM-version of the C164CI is equipped with port drivers, which provide reduced driving capability and reduced control. Please refer to the actual errata sheet for details.
3) 4)
5)
Data Sheet
42
V2.0, 2001-05
C164CI/SI C164CL/SL
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C164CI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C164CI will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to the C164CI. DC Characteristics (Operating Conditions apply)1) Parameter Input low voltage (TTL, all except XTAL1) Input low voltage XTAL1 Input low voltage (Special Threshold) Input high voltage (TTL, all except RSTIN, XTAL1) Input high voltage RSTIN (when operated as input) Input high voltage XTAL1 Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Output low voltage2) Output high voltage5) Symbol Limit Values min. max. 0.2 VDD V - 0.1 0.3 VDD V 2.0 V V V V V mV V V V V nA - - - - - - - Series resistance =0 Unit Test Conditions
VIL
SR -0.5
VIL2 SR -0.5 VILS SR -0.5 VIH
SR 0.2 VDD VDD + + 0.9 0.5 0.5
VIH1 SR 0.6 VDD VDD + VIH2 SR 0.7 VDD VDD +
0.5
VIHS SR 0.8 VDD VDD +
- 0.2 HYS 400 0.5 - 1.0 0.45 - - 200
VOL CC -
-
VOH CC VDD 1.0
IOL IOLmax3) IOL IOLnom3)4) IOH IOHmax3) IOH IOHnom3)4)
0 V < VIN < VDD
VDD 0.45 Input leakage current (Port 5)
IOZ1 CC -
Data Sheet
43
V2.0, 2001-05
C164CI/SI C164CL/SL
DC Characteristics (cont'd) (Operating Conditions apply)1) Parameter Input leakage current (all other) RSTIN inactive current6) RSTIN active current6) RD/WR inact. current9) RD/WR active current ALE inactive current ALE active current
9) 9) 9)
Symbol
Limit Values min. max. 500 -10 - -40 - 40 - -40 - -10 - 20 10
Unit Test Conditions nA A A A A A A A A A A A pF 0.45 V < VIN <
IOZ2 CC - IRSTH7) IRSTL8) IRWH 7) IRWL8) IALEL7) IALEH8) IP4H7) IP4L8) IP0H7) IP0L8) IIL CC CIO CC
- -100 - -500 - 500 - -500 - -100 - -
Port 4 inactive current9) Port 4 active current9) PORT0 configuration current10) XTAL1 input current Pin capacitance11) (digital inputs/outputs)
1)
VDD VIN = VIH1 VIN = VIL VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max VIN = VIHmin VIN = VILmax 0 V < VIN < VDD f = 1 MHz TA = 25 C
Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. For signal levels outside these specifications also refer to the specification of the overload current IOV. For pin RSTIN this specification is only valid in bidirectional reset mode. The maximum deliverable output current of a port driver depends on the selected output driver mode, see Table 10, Current Limits for Port Output Drivers. The limit for pin groups must be respected. As a rule, with decreasing output current the output levels approach the respective supply level (VOL VSS, VOH VDD). However, only the levels for nominal output currents are guaranteed. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 k. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is valid during Reset and during Adapt-mode. The Port 4 current values are only valid for pins P4.3-0, which can act as CS outputs. This specification is valid during Reset if required for configuration, and during Adapt-mode. Not 100% tested, guaranteed by design and characterization.
2) 3)
4)
5)
6) 7) 8) 9)
10) 11)
Data Sheet
44
V2.0, 2001-05
C164CI/SI C164CL/SL
Table 10
Current Limits for Port Output Drivers Maximum Output Current (IOLmax, -IOHmax)1) 10 mA 4.0 mA 0.5 mA Nominal Output Current (IOLnom, -IOHnom)2) 2.5 mA 1.0 mA 0.1 mA
Port Output Driver Mode Strong driver Medium driver Weak driver
1)
An output current above |IOXnom | may be drawn from up to three pins at the same time. For any group of 16 neighboring port output pins the total output current in each direction (IOL and -IOH) must remain below 50 mA. The current ROM-version of the C164CI (step Ax) is equipped with port drivers, which provide reduced driving capability and reduced control. Please refer to the actual errata sheet for details.
2)
Power Consumption C164CI (ROM) (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Idle mode supply current with all peripherals deactivated, PLL off, SDD factor = 32 Sleep and Power-down mode supply current with RTC running Symbol Limit Values min. - - max. Unit Test Conditions RSTIN = VIL fCPU in [MHz]1) RSTIN = VIH1 fCPU in [MHz]1) RSTIN = VIH1 fOSC in [MHz]1)
IDD IIDX
1+ mA 2.5 x fCPU 1+ mA 1.1 x fCPU 500 + A 50 x fOSC 200 + A 25 x fOSC 50 A
IIDO2) - IPDR2) -
-
Sleep and Power-down mode IPDO supply current with RTC disabled
1)
VDD = VDDmax fOSC in [MHz]3) VDD = VDDmax3)
The supply current is a function of the operating frequency. This dependency is illustrated in Figure 9. These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH. This parameter is determined mainly by the current consumed by the oscillator (see Figure 8). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
2)
3)
Data Sheet
45
V2.0, 2001-05
C164CI/SI C164CL/SL
Power Consumption C164CI (OTP) (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Idle mode supply current with all peripherals deactivated, PLL off, SDD factor = 32 Sleep and Power-down mode supply current with RTC running Symbol Limit Values min. - - max. 10 + 3.5 x fCPU Unit Test Conditions mA RSTIN = VIL fCPU in [MHz]1) RSTIN = VIH1 fCPU in [MHz]1) RSTIN = VIH1 fOSC in [MHz]1)
IDD IIDX
5+ mA 1.25 x fCPU 500 + 50 x fOSC 200 + 25 x fOSC 50 A
IIDO2) - IPDR2) -
-
A A
Sleep and Power-down mode IPDO supply current with RTC disabled
1)
VDD = VDDmax fOSC in [MHz]3) VDD = VDDmax3)
The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10. These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH. This parameter is determined mainly by the current consumed by the oscillator (see Figure 8). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
2)
3)
Data Sheet
46
V2.0, 2001-05
C164CI/SI C164CL/SL
A 1500 1250 1000 750 500
I IDOmax
I IDOtyp
I PDRmax
250
I PDOmax
0 0 4 8 12 16 MHz f OSC
MCD04433
Figure 8
Idle and Power Down Supply Current as a Function of Oscillator Frequency
Data Sheet
47
V2.0, 2001-05
C164CI/SI C164CL/SL
I [mA]
100
80
IDD5max IDD5typ
60
40
IIDX5max IIDX5typ
20
10 Figure 9
15
20
25
fCPU [MHz]
Supply/Idle Current as a Function of Operating Frequency for ROM Derivatives
Data Sheet
48
V2.0, 2001-05
C164CI/SI C164CL/SL
I [mA]
IDD5max
100
IDD5typ
80
60
40
IIDX5max IIDX5typ
20
10 Figure 10
15
20
25
fCPU [MHz]
Supply/Idle Current as a Function of Operating Frequency for OTP Derivatives
Data Sheet
49
V2.0, 2001-05
C164CI/SI C164CL/SL
AC Characteristics Definition of Internal Timing The internal operation of the C164CI is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see Figure 11).
Phase Locked Loop Operation
fOSC
TCL
fCPU
TCL Direct Clock Drive
fOSC
TCL
fCPU
TCL Prescaler Operation
fOSC
TCL
fCPU
TCL
MCT04338
Figure 11
Generation Mechanisms for the CPU Clock
The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU. This influence must be regarded when calculating the timings for the C164CI. Note: The example for PLL operation shown in Figure 11 refers to a PLL factor of 4. The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
Data Sheet 50 V2.0, 2001-05
C164CI/SI C164CL/SL
P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 11 associates the combinations of these three bits with the respective clock generation mode. Table 11 C164CI Clock Generation Modes External Clock Input Range2) 2.5 to 6.25 MHz 3.33 to 8.33 MHz 5 to 12.5 MHz 2 to 5 MHz 1 to 25 MHz 6.66 to 16.66 MHz 2 to 50 MHz 4 to 10 MHz Notes Default configuration - - - Direct drive3) - CPU clock via prescaler -
CLKCFG1) CPU Frequency (RP0H.7-5) fCPU = fOSC x F fOSC x 4 111 110 101 100 011 010 001 000
1) 2) 3)
fOSC x 3 fOSC x 2 fOSC x 5 fOSC x 1 fOSC x 1.5 fOSC / 2 fOSC x 2.5
Please note that pin P0.15 (corresponding to RP0H.7) is inverted in emulation mode, and thus also in EHM. The external clock input range refers to a CPU clock range of 10 ... 25 MHz. The maximum frequency depends on the duty cycle of the external clock signal.
Prescaler Operation When prescaler operation is configured (CLKCFG = 001B) the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fOSC. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fOSC for any TCL. Phase Locked Loop When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is enabled and provides the CPU clock (see Table 11). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fOSC x F). With every F'th transition of fOSC the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly.
Data Sheet
51
V2.0, 2001-05
C164CI/SI C164CL/SL
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and Figure 12). For a period of N x TCL the minimum value is computed using the corresponding deviation DN: (N x TCL)min = N x TCLNOM - DN; DN [ns] = (13.3 + N x 6.3)/fCPU [MHz], where N = number of consecutive TCLs and 1 N 40. So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D3 = (13.3 + 3 x 6.3)/25 = 1.288 ns, and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ fCPU = 25 MHz). This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible. Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 12).
Max. jitter DN ns 30 26.5 This approximated formula is valid for 1 < N < 40 and 10 MHz < fCPU < 25 MHz. -- - - 10 MHz
20 16 MHz 20 MHz 25 MHz 10
1 1 10 20 30 40
N
MCD04455
Figure 12
Data Sheet
Approximated Maximum Accumulated PLL Jitter
52 V2.0, 2001-05
C164CI/SI C164CL/SL
Direct Drive When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fOSC so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fOSC. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: TCLmin = 1/fOSC x DCmin (DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated so the duration of 2TCL is always 1/fOSC. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1, 3, ...). Timings that require an even number of TCLs (2, 4, ...) may use the formula 2TCL = 1/fOSC.
Data Sheet
53
V2.0, 2001-05
C164CI/SI C164CL/SL
AC Characteristics External Clock Drive XTAL1 (Operating Conditions apply) Table 12 Parameter External Clock Drive Characteristics Symbol Direct Drive 1:1 min. Oscillator period High time2) Low time2) Rise time2) Fall time2)
1)
Prescaler 2:1 min. 20 6 6 - - max. - - - 5 5 min. 601) 10 10 - -
PLL 1:N max. 5001) - - 10 10
Unit
max. - - - 8 8
tOSC t1 t2 t3 t4
SR 40 SR 203) SR 203) SR - SR -
ns ns ns ns ns
The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. The clock input signal must reach the defined levels VIL2 and VIH2. The minimum high and low time refers to a duty cycle of 50%. The maximum operating freqency (fCPU) in direct drive mode depends on the duty cycle of the clock input signal.
2) 3)
t1 0.5 VDD t2
t3
t4 VIH2 VIL
t OSC
MCT02534
Figure 13
External Clock Drive XTAL1
Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 16 MHz. It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested).
Data Sheet
54
V2.0, 2001-05
C164CI/SI C164CL/SL
A/D Converter Characteristics (Operating Conditions apply) Table 13 Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Calibration time after reset Total unadjusted error Internal resistance of reference voltage source A/D Converter Characteristics Symbol Limit Values min. max. 4.0 Unit Test Conditions
1)
VAREF SR VAGNDSR VAIN SR fBC tC CC tCAL
VSS - 0.1 VAGND
0.5 -
VDD + 0.1 V VSS + 0.2 V VAREF V
6.25 40 tBC + - tS + 2tCPU 3328 tBC 2 - k k pF
-
2)
MHz 3)
4)
tCPU = 1 / fCPU
5)
CC -
TUE CC -
LSB 1)
RAREF SR -
tBC / 60
- 0.25
tBC in [ns]6)7) tS in [ns]7)8)
7)
Internal resistance of analog RASRC SR - source ADC input capacitance
1)
tS / 450
- 0.25 33
CAIN CC -
TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages within the defined voltage range. If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V (i.e. VAREF = VDD = +0.2 V) the maximum TUE is increased to 3 LSB. This range is not 100% tested. The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see IOV specification) does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB.
2)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in
these cases will be X000H or X3FFH, respectively. The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock tBC depend on programming and can be taken from Table 14. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. During the reset calibration conversions can be executed (with the current accuracy). The time required for these conversions is added to the total reset calibration time. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing. Not 100% tested, guaranteed by design and characterization.
3) 4)
5)
6)
7)
Data Sheet
55
V2.0, 2001-05
C164CI/SI C164CL/SL
8)
During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time tS depend on programming and can be taken from Table 14.
Sample time and conversion time of the C164CI's A/D Converter are programmable. Table 14 should be used to calculate the above timings. The limit values for fBC must not be exceeded when selecting ADCTC. Table 14 A/D Converter Computation Table A/D Converter Basic Clock fBC ADCON.13|12 Sample time tS (ADSTC) 00 01 10 11
ADCON.15|14 (ADCTC) 00 01 10 11
fCPU / 4 fCPU / 2 fCPU / 16 fCPU / 8
tBC x 8 tBC x 16 tBC x 32 tBC x 64
Converter Timing Example: Assumptions: Basic clock Sample time Conversion time
fCPU fBC tS tC
= 25 MHz (i.e. tCPU = 40 ns), ADCTC = `00', ADSTC = `00'. = fCPU/4 = 6.25 MHz, i.e. tBC = 160 ns. = tBC x 8 = 1280 ns. = tS + 40 tBC + 2 tCPU = (1280 + 6400 + 80) ns = 7.8 s.
Data Sheet
56
V2.0, 2001-05
C164CI/SI C164CL/SL
Testing Waveforms
2.4 V
1.8 V Test Points
1.8 V
0.45 V
0.8 V
0.8 V
AC inputs during testing are driven at 2.4 V for a logic '1' and 0.45 V for a logic '0'. Timing measurements are made at VIH min for a logic '1' and VIL max for a logic '0'.
MCA04414
Figure 14
Input Output Waveforms
VLoad + 0.1 V
Timing Reference Points
VOH - 0.1 V
VLoad - 0.1 V
VOL + 0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA).
MCA00763
Figure 15
Float Waveforms
Data Sheet
57
V2.0, 2001-05
C164CI/SI C164CL/SL
Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 15 Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Memory Cycle Variables Symbol Values TCL x 2TCL x (15 - ) 2TCL x (1 - )
tA tC tF
Note: Please respect the maximum operating frequency of the respective derivative. AC Characteristics Multiplexed Bus (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) max. - - - - min. TCL - 10 + tA TCL - 16 + tA TCL - 10 + tA TCL - 10 + tA -10 + tA - - 2TCL - 10 + tC max. - - - - - 6 TCL + 6 - ns ns ns ns ns ns ns ns
t5 t6 t7 t8 t9
CC 10 + tA CC 4 + tA CC 10 + tA CC 10 + tA
CC -10 + tA - 6 26 -
t10 CC - t11 CC - t12 CC 30 + tC
Data Sheet
58
V2.0, 2001-05
C164CI/SI C164CL/SL
Multiplexed Bus (cont'd) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR max. - 20 + tC 40 + tC 40 + tA + tC min. 3TCL - 10 + tC - - - max. - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + tF - - - - 10 - tA 3TCL - 20 + tC + 2tA - - ns ns ns ns ns ns ns ns ns ns ns ns ns
t13 CC 50 + tC t14 SR - t15 SR - t16 SR - t17 SR - t18 SR 0 t19 SR - t22 CC 20 + tC t23 CC 26 + tF
50 + 2tA - + tC - 26 + tF - - - - 10 - tA 40 + tC + 2tA - - 0 - 2TCL - 20 + tC 2TCL - 14 + tF 2TCL - 14 + tF 2TCL - 14 + tF -4 - tA -
ALE rising edge after RD, t25 CC 26 + tF WR Address hold after RD, WR ALE falling edge to CS1) CS low to Valid Data In1)
t27 CC 26 + tF t38 CC -4 - tA t39 SR -
CS hold after RD, WR1) ALE fall. edge to RdCS, WrCS (with RW delay)
t40 CC 46 + tF t42 CC 16 + tA
3TCL - 14 + tF TCL - 4 + tA
ns ns
Data Sheet
59
V2.0, 2001-05
C164CI/SI C164CL/SL
Multiplexed Bus (cont'd) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. ALE fall. edge to RdCS, WrCS (no RW delay) max. - 0 20 16 + tC 36 + tC - - - - 20 + tF - - min. -4 + tA - - - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14 + tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF max. - 0 TCL 2TCL - 24 + tC 3TCL - 24 + tC - - - - 2TCL - 20 + tF - - ns ns ns ns ns ns ns ns ns ns ns ns
t43 CC -4 + tA
Address float after RdCS, t44 CC - WrCS (with RW delay) Address float after RdCS, t45 CC - WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS
1)
t46 SR - t47 SR - t48 CC 30 + tC t49 CC 50 + tC t50 CC 26 + tC t51 SR 0 t52 SR - t54 CC 20 + tF t56 CC 20 + tF
These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below).
Data Sheet
60
V2.0, 2001-05
C164CI/SI C164CL/SL
t5
ALE
t16
t25
t38
CSxL A21-A16 (A15-A8) BHE, CSxE
t39
t40
t17
Address
t27 t54 t19 t18
t6
t7
Read Cycle BUS Address
Data In
t8
RD
t10 t14 t44 t12 t46 t48 t51 t52
t42
RdCSx
Write Cycle BUS Address Data Out
t23 t56 t22 t12 t50 t48
t8
WR, WRL, WRH WrCSx
t10
t42
t44
Figure 16
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE
61 V2.0, 2001-05
Data Sheet
C164CI/SI C164CL/SL
t5
ALE
t16
t25
t38 t39
CSxL
t40
A21-A16 (A15-A8) BHE, CSxE Read Cycle BUS
t17
Address
t27 t54 t19 t18
t6
t7
Address
Data In
t8
RD
t10 t14 t4 t12 t46 t48 t51 t52
t42
RdCSx
Write Cycle BUS Address Data Out
t23 t56 t22 t12 t50 t48
t8
WR, WRL, WRH WrCSx
t10
t42
t44
Figure 17
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE
62 V2.0, 2001-05
Data Sheet
C164CI/SI C164CL/SL
t5
ALE
t16
t25
t38
CSxL
t39
t40
A21-A16 (A15-A8) BHE, CSxE Read Cycle BUS
t17
Address
t27 t54 t19 t18
t6
t7
Address
Data In
t9
RD
t11
t15 t13 t51 t52
t43
RdCSx
t45
t47 t49
Write Cycle BUS Address Data Out
t23 t56 t11 t22 t13 t50 t49
t9
WR, WRL, WRH WrCSx
t43
t45
Figure 18
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE
63 V2.0, 2001-05
Data Sheet
C164CI/SI C164CL/SL
t5
ALE
t16 t38 t39
t25
t40
CSxL
A21-A16 (A15-A8) BHE, CSxE Read Cycle BUS
t17
Address
t27 t54 t19 t18
t6
t7
Address
Data In
t9
RD
t11
t15 t13 t51 t52
t43
RdCSx
t45
t47 t49
Write Cycle BUS Address Data Out
t23 t56 t9 t11 t22 t13 t50 t49
WR, WRL, WRH WrCSx
t43
t45
Figure 19
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE
64 V2.0, 2001-05
Data Sheet
C164CI/SI C164CL/SL
AC Characteristics Demultiplexed Bus (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay1)) Data float after RD rising edge (no RW-delay1)) max. - - - min. TCL - 10 + tA TCL - 16 + tA TCL - 10 + tA -10 + tA 2TCL - 10 + tC 3TCL - 10 + tC - - - - 0 max. - - - - - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + 22tA + tF1) TCL - 10 + 22tA + tF1) ns ns ns ns ns ns ns ns ns ns ns ns
t5 t6 t8 t9
CC 10 + tA CC 4 + tA CC 10 + tA
CC -10 + tA - - - 20 + tC 40 + tC 40 +
t12 CC 30 + tC t13 CC 50 + tC t14 SR - t15 SR - t16 SR - t17 SR - t18 SR 0 t20 SR -
tA + tC
50 + 2tA + tC -
26 + - 1) 2tA + tF 10 + - 1) 2tA + tF
t21 SR -
ns
Data Sheet
65
V2.0, 2001-05
C164CI/SI C164CL/SL
Demultiplexed Bus (cont'd) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. Data valid to WR Data hold after WR max. - - - - 10 - tA 40 + tC + 2tA - - - 16 + tC 36 + tC - - - - 20 + tF min. 2TCL - 20 + tC TCL - 10 + tF -10 + tF 0 + tF -4 - tA - TCL - 14 + tF TCL - 4 + tA -4 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14 + tC 0 - max. - - - - 10 - tA 3TCL - 20 + tC + 2tA - - - 2TCL - 24 + tC 3TCL - 24 + tC - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t22 CC 20 + tC t24 CC 10 + tF
ALE rising edge after RD, t26 CC -10 + tF WR Address hold after WR2) ALE falling edge to CS3) CS low to Valid Data In3) CS hold after RD, WR3)
t28 CC 0 + tF t38 CC -4 - tA t39 SR - t41 CC 6 + tF
ALE falling edge to RdCS, t42 CC 16 + tA WrCS (with RW-delay) ALE falling edge to RdCS, t43 CC -4 + tA WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay)1)
t46 SR - t47 SR - t48 CC 30 + tC t49 CC 50 + tC t50 CC 26 + tC t51 SR 0 t53 SR -
2TCL - 20 ns + 2tA + tF1)
Data Sheet
66
V2.0, 2001-05
C164CI/SI C164CL/SL
Demultiplexed Bus (cont'd) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. Data float after RdCS (no RW-delay)1) Address hold after RdCS, WrCS Data hold after WrCS
1) 2)
max. 0 + tF - -
min. - -6 + tF
max. TCL - 20 ns 1) + 2tA + tF - ns ns
t68 SR - t55 CC -6 + tF t57 CC 6 + tF
TCL - 14 + -
tF
RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral). Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below).
3)
Data Sheet
67
V2.0, 2001-05
C164CI/SI C164CL/SL
t5
ALE
t16
t26
t38
CSxL
t39
t41
A21-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0
t17
Address
t28 t55 t20 t18
Data In
t6
t8
RD
t14 t12 t51 t53
t42
RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH
t24
Data Out
t57 t8 t22 t12 t50 t48
t42
WrCSx
Figure 20
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE
68 V2.0, 2001-05
Data Sheet
C164CI/SI C164CL/SL
t5
ALE
t16 t38 t39
t26
t41
CSxL
A21-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0
t17
Address
t28 t55 t20 t18
Data In
t6
t8
RD
t14 t12 t51 t53
t42
RdCSx
t46 t48
Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH
t24
Data Out
t57 t8 t22 t12 t50 t48
t42
WrCSx
Figure 21
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE
69 V2.0, 2001-05
Data Sheet
C164CI/SI C164CL/SL
t5
ALE
t16
t26
t38
CSxL
t39
t41
A21-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0 RD
t17
Address
t28 t55 t21 t18
Data In
t6
t9 t15 t43 t13 t47 t49 t51 t68
RdCSx
Write Cycle BUS (D15-D8) D7-D0 WR, WRL,WRH
t24
Data Out
t9
t57 t22 t13 t50 t49
t43
WrCSx
Figure 22
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE
70 V2.0, 2001-05
Data Sheet
C164CI/SI C164CL/SL
t5
ALE
t16 t38 t39
t26
t41
CSxL
A21-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0
t17
Address
t28 t55 t21 t18
Data In
t6
t9
RD
t15 t13 t51 t68
t43
RdCSx
t47 t49
Write Cycle BUS (D15-D8) D7-D0
t24
Data Out
t57 t9 t22 t13 t50 t49
WR, WRL, WRH
t43
WrCSx
Figure 23
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE
71 V2.0, 2001-05
Data Sheet
C164CI/SI C164CL/SL
AC Characteristics CLKOUT (Operating Conditions apply) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge max. 40 - - 4 4 10 + tA min. 2TCL TCL - 6 TCL - 10 - - 0 + tA max. 2TCL - - 4 4 10 + tA ns ns ns ns ns ns
t29 t30 t31 t32 t33 t34
CC 40 CC 14 CC 10 CC - CC - CC 0 + tA
Running cycle1)
t32 t33 t30 t34 t31 t29
MUX/Tristate 3)
CLKOUT
ALE
4)
Command RD, WR Figure 24 CLKOUT Timing
2)
Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay. 3) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 4) The next external bus cycle may start here.
Data Sheet
72
V2.0, 2001-05
C164CI/SI C164CL/SL
External XRAM Access If XPER-Share mode is enabled the on-chip XRAM of the C164CI can be accessed (during hold states) by an external master like an asynchronous SRAM. Table 16 Parameter Address setup time before RD/WR falling edge Address hold time after RD/WR rising edge Data output valid delay after address latched Data turn off delay after RD rising edge Write data setup time before WR rising edge WR pulse width WR signal recovery time Write Write data hold time after WR rising edge Read Data turn on delay after RD falling edge XRAM Access Timing (Operating Conditions apply) Symbol Limit Values min. max. - - - 37 10 - - - - ns ns ns ns ns ns ns ns ns Unit
t40 t41 t42 t43 t44 t45 t46 t47 t48
SR 4 SR 0 CC 2 CC - CC 0 SR 10 SR 1 SR 18 SR t40
t40
Address
t41
t47
Command (RD, WR)
t48
t46 t45
Write Data
t43 t42
Read Data
MCT04423
t44
Figure 25
External Access to the XRAM
Data Sheet
73
V2.0, 2001-05
C164CI/SI C164CL/SL
Package Outlines P-MQFP-80-7 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 74
Dimensions in mm V2.0, 2001-05
GPM05249
Infineon goes for Business Excellence
"Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction."
Dr. Ulrich Schumacher
http://www.infineon.com
Published by Infineon Technologies AG

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